Aprisa and Apogee place and route tools ready for early customer engagement
SANTA CLARA, CA – November 9, 2015 – ATopTech, a leader in next-generation physical design solutions, today announced their Aprisa™ and Apogee™ Place & Route tools are now enabled for the current version of the GLOBALFOUNDRIES 22FDX™ platform reference flow. GLOBALFOUNDRIES has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage needed to create the next-generation chips for mainstream mobile, IoT and networking applications.
ATopTech tools support the 22FDX design rules and methodology for forward and reverse body bias (FBB/RBB) to optimize the performance/power trade-offs, implant-aware and continuous diffusion-aware placement, and Inter-layer Non-Default-Rule for High Voltage nets. Ongoing enhancements to ATopTech's Aprisa™ and ApogeeTM P&R tools will provide designers with capability to intelligently and dynamically tune the power and performance of the next-generation system-on-chip (SoC) designs.
"Our collaboration with ATopTech enables their products to help customers fully leverage the benefits of the GLOBALFOUNDRIES 22FDX platform," said Pankaj Mayor, vice president of Business Development at GLOBALFOUNDRIES. "The work we are doing together on the 22FDX reference flow will enable designers to deliver differentiated products with the optimal balance of power and performance."
"ATopTech is ready to help joint customers meet the ultra-low-power requirements of the newest generation of connected devices," said Jue-Hsien Chern, CEO of ATopTech. "Working with GLOBALFOUNDRIES, we strive to deliver the latest technology customers expect from ATopTech."
Aprisa is a complete place-and-route (P&R) engine, including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common "analysis engines," such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
Apogee is a full-featured, top-level physical implementation tool that includes prototyping, floorplanning, and chip assembly. The unified hierarchical database enables a much more streamlined hierarchical design flow. Unique in-hierarchy-optimization (iHO) technology helps to close top-level timing during chip assembly through simultaneous optimization at top level and at blocks, reducing the turnaround time for top-level timing closure from weeks to days.
ATopTech, Inc. is the technology leader in IC physical design. ATopTech's technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com