Aprisa is a complete full-functioned block-level place and route (P&R) system with placement, clock tree synthesis, routing, optimization and embedded analysis engines. It supports standard data inputs and outputs, such as Verilog, SDC, LEF/DEF, Liberty, and GDSII. The state-of-the-art technologies and tightly integrated functions ensure superior quality-of-result and competitive runtime for IC design projects.
The core of the technology is the detailed-route-centric architecture and the hierarchical database. Built upon that, there are common “analysis engines”, such as RC extraction, DRC engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, SI and MCMM analysis. Those engines support the precision optimization engine which is consistently used across every P&R step. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process and avoid the exploding runtime issues with modern nanoscale design.
- *New* detailed-route-centric architecture and hierarchical database
- Mulit-threaded and distributed engines
- Capacity up to hundreds of millions of gates
- Up to 2x faster "time to design closure"
- Timing consistency through the whole flow
- Homogenous cross-level design environment
- In-Hierarchy Optimization (iHO) for top-level timing closure
- Easier to support hierarchical flow
- Easier to apply hierarchical ECO
- Faster and easier top-level timing closure without long cycle of timing re-budgeting and timing model updating
- Adaptive MCMM Optimization for all stages in the flow
- Optimize designs efficiently for all design corners and operational modes and for multiple design targets
- Full utilization of available CPU’s and memory for best runtime and QoR
- Progressive MCMM CTS
- Skewgroup-based CTS
- Slack-driven CTS
- Multi-point CTS
- Support for mesh and H-tree
- Power aware clock tree optimization with useful skew
- Efficiently Balanced clock trees for all modes and corners
- Flexibility to leverage skewgroup information for even more efficient clock trees
- Fewer buffers for clock trees
- and 20% less power and area and better timing closure
- SI-aware placement optimization and global route optimization
- Full support for AOCV/LOCV/POCV and LVF
- In-route DFM with wire spreading, metal fill and DFM via insertion
- Timing-driven DFM via insertion
- Signal net EM analysis and optimization
- Fewer rounds of design iterations and ECO’s
- Better quality of result (QoR)
- Shorter overall turn-around time (TaT)
- Power-centric optimization
- Ensure more low leakage cells are used for best possible power
- Color-aware routing for 20nm and below
- Scalable multi-threaded routing
- Superior turn-around times
- No iterations needed to sign-off tools for G0 violation checking
- Full support of both UPF and CPF with Intelligent Always-On buffer insertion and built-in power-spec checker
- Simplify multi-power-domain designs
- Reduce usage of Always-On buffers for better power consumption and rout-ability
- Ensure power device insertion comply to the specification
Industry's First Detailed-Route-Centric P&R Architecture
Detailed-Route-Centric architecture is Avatar's newest technology which enables efficient and frequent detailed route layers, patterns, congestions, pin-access, etc. to be available throughout the place and route flow, which reduce the number of place and route iterations and accelerate design closure.
Interconnect Centric "Precision Optimization"
Precision optimization allows Aprisa to do optimization based on much more accurate information than tools in the past. Rather than using very pessimistic models or using a margin based approach, precision optimization is based on very accurate 2.5D parasitic extraction (which is multi-threaded) and SI analysis that is based on near detail route level accuracy. This optimization happens through out the flow, during placement, CTS, and both global route and detailed routing.
Aprisa provides an easy-to-use floor-planner that enables fast analysis of design hierarchy. Automation of many of the traditionally manual tasks such as manual macro placement and blockage creation helps the designers converge on an optimal floor-plan much faster. Common placement, routing, and timing engines mean good correlation for congestion and timing from floorplanning stage all the way through the final routing stage. The rich feature set includes:
- Channeled and channel-less floorplans, or a mix of both
- Rectilinear floorplans
- Multiple libraries, and multi-height standard cells
- Parametric multit-headed routing for power/ground grid creation
- Automatic placement blockage generator
- Automatic macro placer with grouping and legalization capabilities
- Pin optimization and legalization
- Pad ring placement
- Hierarchical fly line analysis
- Logical hierarchy browser and cross-probing of logical modules to layout
Placement and Optimization
Aprisa´s placement technology is a timing and congestion driven analytical based placer. The placer calls the timing analysis engine frequently to dynamically obtain and update the best net weightings throughout the flow. The placement and optimization engines iterates intelligently between wire-length, routing congestion, area, leakage power and other critical factors to achieve optimal timing, area and power for the block/configuration under consideration. Support includes:
- Complex floorplan / placement constraints including rectilinear regions, multi-height cells, and mixed/overlapping sites
- Efficient High Fan-out Synthesis
- Intelligent Low power(leakage) optimization
- Area Recovery
- Switching activity aware placement and optimization
- Always-on buffering and retention cell placement
- OCV aware placement
- Useful skew based placement optimization
- Multi-corner and multi-mode placement optimization
Clock Tree Synthesis (CTS) and Optimization
Aprisa´s sophisticated CTS engine handles scenarios for complex designs. Optimizing for both area and leakage power, it minimizes the number of buffers. The CTS engine does optimization for skew, minimization of global, local and inter-clock skew and supports useful local skew control for overall timing optimization. In addition, the engine supports:
- Cluster-based clock trees or meshes
- Gated and generated clocks
- Synchronization of generated clock pins
- Automatic clock gate cloning and de-cloning
- Matching of latency targets specified by user for any pins
- Automatic creation of special routing constraints (layer, double width/spacing/via, shielding, etc.)
- Low-Power Clock Tree Synthesis
- Multi-corner and multi-mode clock tree synthesis and clock optimization
- Level-balanced Clock Tree Synthesis
- Route-based clock tree optimization
Additionally, the Clock Tree Browser GUI provides sophisticated features such as cross-probing and editing on the fly such as resizing clock buffers or moving clock buffer/leaf cell to different levels. It provides detailed delay, transition, skew and load information for each node; and can find or highlight any max or min path to calculate local skew.
Timing and Analysis
Aprisa includes a next generation timing analysis engine with many advanced features.
- Very fast, typically 5 minutes per million instances
- Read SDC natively without any translation
- Native OCV timing analysis
- CRPR Support (clock convergence pessimism removal)
- Timing browser (see diagram)
Multi-corner Multi-mode Analysis
The ever increasing significance of the PVT (Process, Voltage, and Temperature) variation from today's trend in semiconductor design demands more design corners to be signed-off. The timing and functionality of complex designs also need to be verified and optimized for multiple operation modes. Aprisa's advanced MCMM analysis ensures designs are efficiently optimized for all modes and all corners, and for all QoR design metrics, throughout the design process.
- Sophisticated mechanism: unlimited number of scenarios are analyzed in either sequential, multi-threaded, or distributed mode
- Adaptive MCMM automatically groups scenarios and analyzes them in mixed sequential/multi-threaded mode, thus achieves optimal balance of memory usage and run time for any given computation resources.
- Flexible scenario creation: each scenario has its own mode (SDC), library corner, and RC condition.
- Native MCMM throughout the entire flow: place_opt, cts, post_cts_opt, groute_opt and droute_opt for predictable design closure
- Allows different set of "effective scenarios" to be analyzed at different stage of the flow
- Progressive MCMM CTS automatically merges different modes and considers crossing of clock domains from different mode.
Global Route and Optimization
Aprisa's fast global route engine can route millions of nets in minutes. The global route includes track assignment so that near detailed route information can be used to generate delays and signal integrity information.
Combined with precision optimization sizing, buffering, and wire spreading can all be looked at concurrently to achieve the best possible solution. All of this is done with MCMM timing. The key is to eliminate the problems such as congestion and signal integrity issues before the detailed route phase. The unique feature of this step is that it is trying to address gross signal-integrity problems during global route stage. This allows more changes than is possible during post-route stage. Support includes:
- Iterative fixing of timing and routing to achieve timing closure
- SI aware timing engine enabling fixing the noise violations where they happen i.e. not an after-thought to fix the SI violations.
- Route aware area recovery
- Route aware leakage power optimization
- Metal fill emulation to get accurate prediction of final timing
Detailed Route and Optimization
Aprisa's detailed router is a hybrid technology. Although the router is gridded, it can route to any off-grid pin when necessary. Unlike other routers which handle lot of DRC as an afterthought, Aprisa router handles all the DRC violations while actually routing the. Coupled with the router is the precision optimization engine to do route based optimization concurrently to fix SI aware timing.
- Multi-threaded engine with near linear performance. An 8 cpu machine will achieve 7-7.5X the performance of a single CPU. Routes 250K instance in about 5 minutes on an 8 CPU machine.
- Supports all 90/65/40/28nm design rules
- Supports special routing rules such as double wide, double spaced, shielding, double vias, etc.
- Support for DFM issues such as wire-spreading, double-vias, and complex design rules such as end-of-line spacing/extension, min edge, min enclosure, etc. All these rules are honored in-route and not as a post-processing step.
- Electro migration(EM) aware routing and fixing
- Router minimizes unnecessary jogs to achieve shortest wire length with optimal via count.
- Support for route aware area and power optimization.
- Metal fill emulation to get accurate prediction of final timing.
- No separate step need to fix SI related timing violation; they get concurrently fixed while doing route based optimization