Wed, Oct 3rd, 2018 — Deep Chip/ CooleyDeepChip: Avatar at TSMC OIP Questions
My spies reported Avatar (Atoptech) was launching its own REV2 remake of their Aprisa PnR tool at TSMC OIP in Santa Clara on Wednesday (today). Word is both Mellanox and eSilicon will be speaking up for this Aprisa REV2
but it's not know whether they'll be in the Avatar TSMC OIP booth or not.
Thu, Jul 26th, 2018 — Semi WikiAprisa & Apogee: The New Avatars
Earlier physical optimization impacts a design QoR gain and can disclose potential hurdles in dealing with unknown design variants such as new IP inclusion or new process node issues. Along the RTL-to-GDS2 implementation continuum, a left-shift move requires a robust modeling and proper context captures in order to produce meaningful outcomes.
Fri, Jun 29th, 2018 — EE TimesEDA Start-up Rises From the Ashes of ATopTech
SAN FRANCISCO — A startup, formed from the auctioned assets of ATopTech, showed up at the Design Automation Conference (DAC) here this week open for business and with two well-respected EDA veterans newly added to its leadership team.
Avatar Integrated Systems features substantially all of the technology of ATopTech, including the popular Aprisa and Apogee place-and-route tools used by a number of chip companies. The company also features most of the former employees of ATopTech — including ATopTech co-founder and chief architect Ping San Tzeng — as well as former Cadence Design Systems executives Chi-Ping Hsu and Charlie Huang.
Tue, Jun 26th, 2018 — Electronics WeeklyAvatar planning tools are based around unified hierarchical database
The tools are built on ATopTech technologies which were the subject of a lawsuit brought by Synopsys. Following that, the tools were rebuilt, the command which had been the same as the Synopsys command was changed, explained Lily Cheng, manager of applications engineering, Avatar.